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integrated circuit systems, inc. preliminary product preview ics95v857-xxx 0674i?03/28/03 block diagram 2.5v wide range frequency clock driver (33mhz - 233mhz) pin configuration 48-pin tssop/tvsop recommended application: ddr memory modules / zero delay board fan out product description/features: low skew, low jitter pll clock driver 1 to 10 differential clock distribution (sstl2) feedback pins for input to output synchronization pd# for power management spread spectrum-tolerant inputs auto pd when input signal removed choice of static phase offset available, for easy board tuning; - xxx = device pattern number for options listed below. - ics95v857 ............. 0ps - ics95v857-130 .. +50ps specifications: meets or exceeds jedec standard #82-1 for registered ddr clock driver. meets or exceeds proposed ddr1-400 specifications covers all ddr1 speed grades switching characteristics: cycle - cycle jitter (>100mhz):<50ps output - output skew: <30ps output rise and fall time: 650ps - 950ps duty cycle: 49.5% - 50.5% s t u p n is t u p t u o e t a t s l l p d d v a# d pt n i _ k l cc n i _ k l ct k l cc k l ct t u o _ b fc t u o _ b f d n gh l h lh l h f f o / d e s s a p y b d n gh h l hl h l f f o / d e s s a p y b v 5 . 2 ) m o n ( ll hzzz z f f o v 5 . 2 ) m o n ( lh lzzz z f f o v 5 . 2 ) m o n ( hl hlhl h n o v 5 . 2 ) m o n ( hh l hlh l n o v 5 . 2 ) m o n ( x) z h m 0 2 < ) 1 ( zz z z f f o functionality pll fb_int fb_inc clk_inc clk_int pd# control logic fb_outt fb_outc clkt0 clkt1 clkt2 clkt3 clkt4 clkt5 clkt6 clkt7 clkt8 clkt9 clkc0 clkc1 clkc2 clkc3 clkc4 clkc5 clkc6 clkc7 clkc8 clkc9 6.10 mm body, 0.50 mm pitch = tssop 4.40 mm body, 0.40 mm pitch = tvsop gnd clkc0 clkt0 vdd clkt1 clkc1 gnd gnd clkc2 clkt2 vdd vdd clk_int clk_inc vdd avdd agnd gnd clkc3 clkt3 vdd clkt4 clkc4 gnd gnd clkc5 clkt5 vdd clkt6 clkc6 gnd gnd clkc7 clkt7 vdd pd# fb_int fb_inc vdd fb_outc fb_outt gnd clkc8 clkt8 vdd clkt9 clkc9 gnd ics95v857-xxx 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 product preview documents contain information on new products in the sampling or preproduction phase of development. characteristic data and o ther specifications are subject to change without notice.
2 ics95v857-xxx preliminary product preview 0674i?03/28/03 pin configuration 40-pin mlf 56-ball bga gnd clkc2 clkt2 vdd clk_int clk_inc vdd avdd agnd gnd clkc7 clkt7 vdd pd# fb_int fb_inc vdd vdd fb_outc fb_outt clkc3 clkt3 vdd clkt4 clkc4 clkc9 clkt9 vdd clkt8 clkc8 clkc1 clkt1 vdd clkt0 clkc0 clkc5 clkt5 vdd clkt6 clkc6 1 10 11 20 21 30 29 40 ics95v857 a b 123456 c d e f g h j k 12345 6 a clkt0 clkc0 gnd gnd clkc5 clkt5 b clkc1 clkt1 vdd vdd clkt6 clkc6 c gnd gnd nc nc gnd gnd d clkt2 clkc2 nc nc clkc7 clkt7 e vdd vdd nb nb vdd pd# f clk_int clk_inc nb nb fb_inc fb_int g vdd avdd nc nc fb_outc vdd h agnd gnd nc nc gnd fb_outt j clkc3 clkt3 vdd vdd clkt8 clkc8 k clkt4 clkc4 gnd gnd clkc9 clkt9
3 ics95v857-xxx preliminary product preview 0674i?03/28/03 pin descriptions r e b m u n n i pe m a n n i pe p y tn o i t p i r c s e d , 1 2 , 5 1 , 2 1 , 1 1 , 4 , 5 4 , 8 3 , 4 3 , 8 2 d d vr w pv 5 . 2 y l p p u s r e w o p , 5 2 , 4 2 , 8 1 , 8 , 7 , 1 8 4 , 2 4 , 1 4 , 1 3 d n gr w pd n u o r g 6 1d d v ar w pv 5 . 2 , y l p p u s r e w o p g o l a n a 7 1d n g ar w p. d n u o r g g o l a n a , 6 4 , 4 4 , 9 3 , 9 2 , 7 2 3 , 5 , 0 1 , 0 2 , 2 2 ) 0 : 9 ( t k l ct u o. s t u p t u o r i a p l a i t n e r e f f i d f o k c o l c " e u r t " , 7 4 , 3 4 , 0 4 , 0 3 , 6 2 2 , 6 , 9 , 9 1 , 3 2 ) 0 : 9 ( c k l ct u o. s t u p t u o r i a p l a i t n e r e f f i d f o s k c o l c " y r a t n e m e l p m o c " 4 1c n i _ k l cn it u p n i k c o l c e c n e r e f e r " y r a t n e m e l p m o c " 3 1t n i _ k l cn it u p n i k c o l c e c n e r e f e r " e u r t " 3 3c t u o _ b ft u o t i . k c a b d e e f l a n r e t x e r o f d e t a c i d e d , t u p t u o k c a b d e e f " y r a t n e m e l p m o c " d e r i w e b t s u m t u p t u o s i h t . k l c e h t s a y c n e u q e r f e m a s e h t t a s e h c t i w s . c n i _ b f o t 2 3t t u o _ b ft u o s e h c t i w s t i . k c a b d e e f l a n r e t x e r o f d e t a c i d e d , t u p t u o k c a b d e e f " " e u r t " o t d e r i w e b t s u m t u p t u o s i h t . k l c e h t s a y c n e u q e r f e m a s e h t t a . t n i _ b f 6 3t n i _ b fn i r o f l l p l a n r e t n i e h t o t l a n g i s k c a b d e e f s e d i v o r p , t u p n i k c a b d e e f " e u r t " . r o r r e e s a h p e t a n i m i l e o t t n i _ k l c h t i w n o i t a z i n o r h c n y s 5 3c n i _ b fn i l l p l a n r e t n i e h t o t l a n g i s s e d i v o r p , t u p n i k c a b d e e f " y r a t n e m e l p m o c " . r o r r e e s a h p e t a n i m i l e o t c n i _ k l c h t i w n o i t a z i n o r h c n y s r o f 7 3# d pn it u p n i s o m c v l . n w o d r e w o p this pll clock buffer is designed for a v dd of 2.5v, an av dd of 2.5v and differential data input and output levels. the ics95v857 is a zero delay buffer that distributes a differential clock input pair (clk_inc, clk_int) to ten differential pair of clock outputs (clkt[0:9], clkc[0:9]) and one differential pair feedback clock output (fb_out, fb_outc). the clock outputs are controlled by the input clocks (clk_inc, clk_int), the feedback clocks (fb_int, fb_inc) the 2.5-v lvcmos input (pd#) and the analog power input (av dd ). when input (pd#) is low while power is applied, the receivers are disabled, the pll is turned off and the differential clock outputs are tri-stated. when av dd is grounded, the pll is turned off and bypassed for test purposes. when the input frequency is less than the operating frequency of the pll, appproximately 20mhz, the device will enter a low power mode. an input frequency detection circuit on the differential inputs, independent from the input buffers, will detect the low frequency condition and perform the same low power features as when the (pd#) input is low. when the input frequency increases to greater than approximately 20 mhz, the pll will be turned back on, the inputs and outputs will be enabled and pll will obtain phase lock between the feedback clock pair (fb_int, fb_inc) and the input clock pair (clk_inc, clk_int). the pll in the ics95v857 clock driver uses the input clocks (clk_inc, clk_int) and the feedback clocks (fb_int, fb_inc) provide high-performance, low-skew, low-jitter output differential clocks (clkt [0:9], clkc [0:9]). the ics95v857 is also able to track spread spectrum clock (ssc) for reduced emi. the ics95v857 is characterized for operation from 0c to 85c.
4 ics95v857-xxx preliminary product preview 0674i?03/28/03 absolute maximum ratings supply voltage (vdd & avdd). . . . . . . . . . . -0.5v to 4.6v logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . gnd ?0.5 v to v dd + 0.5 v ambient operating temperature . . . . . . . . . . 0c to +85c storage temperature . . . . . . . . . . . . . . . . . . . ?65c to +150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. electrical characteristics - input/supply/common output parameters t a = 0 - 85c; supply voltage a vdd , v dd = 2.5 v +/- 0.2v (unless otherwise stated) parameter symbol conditions min typ max units input high current i ih v i = v dd or gnd 5 a input low current i il v i = v dd or gnd 5 a i dd2. 5 c l = 0pf @ 200mhz 145 ma i ddpd c l = 0pf 100 a high impedance out p ut current i oz v dd = 2.7v, vout = v dd or gnd 10 ma input clamp voltage v ik v dd = 2.3v iin = -18ma -1.2 v i oh = -1 ma v dd - 0.1 v i oh = -12 ma 1.7v v i ol =1 ma 0.1 v i oh =12 ma 0.6 v input capacitance 1 c in v i = gnd or v dd 2.5 3.5 pf 1 guaranteed b y desi g n at 233mhz, not 100% tested in production. operating supply current high-level output voltage v oh low-level output voltage v ol
5 ics95v857-xxx preliminary product preview 0674i?03/28/03 recommended operating condition ( see note1 ) t a = 0 - 85c; supply voltage avdd, vdd = 2.5 v +/- 0.2v (unless otherwise stated) parameter symbol conditions min typ max units supply voltage v dd , a vdd 2.3 2.7 v clkt, clkc, fb_inc v dd /2 - 0.18 v pd# -0.3 0.7 v clkt, clkc, fb_inc v dd /2 + 0.18 v pd# 1.7 v dd + 0.6 v dc input signal voltage (note 2) -0.3 v dd v dc - clkt, fb_int 0.36 v dd + 0.6 v ac - clkt, fb_int 0.7 v dd + 0.6 v output differential cross - voltage (note 4) v ox v dd /2 - 0.15 v dd /2 + 0.15 v input differential cross- volta g e (note 4) v ix v dd /2 - 0.2 v dd /2 + 0.2 v high level output current i oh -4.5 ma low level output current i ol 4.5 ma input slew rate s r 14v/ns operating free-air temperature t a 085c differential input signal voltage (note 3) v id low level input voltage v il high level input voltage v ih notes: 1. unused inputs must be held high or low to prevent them from floating. 2. dc input signal voltage specifies the allowable dc execution of differential input. 3. differential inputs signal voltages specifies the differential voltage [vtr-vcp] required for switching, where vt is the true input level and vcp is the complementary input level. 4. differential cross-point voltage is expected to track variations of v cc and is the voltage at which the differential signal must be crossing.
6 ics95v857-xxx preliminary product preview 0674i?03/28/03 notes: 1. refers to transition on noninverting output in pll bypass mode. 2. while the pulse skew is almost constant over frequency, the duty cycle error increases at higher frequencies. this is due to the formula: duty cycle=t wh /t c , where the cycle (t c ) decreases as the frequency goes up. 3. switching characteristics guaranteed for application frequency range. 4. static phase offset shifted by design. timing requirements t a = 0 - 85c; supply voltage a vdd , v dd = 2.5 v +/- 0.2v (unless otherwise stated) parameter symbol conditions min max units max clock frequency freq op 2.5v+ 0.2v @ 25 o c 33 233 mhz application frequency range freq app 2.5v+ 0.2v @ 25 o c 95 170 mhz input clock duty cycle d tin 40 60 % clk stabilization t stab 100 s switching characteristics parameter symbol condition min typ max units low-to high level propa g ation dela y time t plh 1 clk_in to any output 5.5 ns high-to low level propagation delay time t pll 1 clk_in to any output 5.5 ns output enable time t en pd# to any output 5 ns output disable time tdis pd# to any output 5 ns period jitter t j it (p er ) 100/125/133/167/200mhz -40 40 ps half-period jitter t(jit_hper) 100/133/167/200mhz -50 50 ps input clock slew rate t sl ( i ) 14v/ns output clock slew rate t sl ( o ) 12.5v/ns cycle to cycle jitter 1 t c y c -t c y c 100/125/133/167/200mhz 50 ps phase error t (p hase error ) 4 -50 0 50 ps output to output skew t skew 30 ps duty cycle d c 2 100mhz to 200mhz 49.5 50.5 % rise time, fall time tr, tf load = 120 ? /16pf 650 800 950 ps
7 ics95v857-xxx preliminary product preview 0674i?03/28/03 gnd ics95v857 v dd v dd /2 v (clkc) v (clkc) scope c=14p f -v dd/2 -v dd/2 -v dd/2 v dd/2 z=60 ? z=60 ? z=50 ? z=50 ? r=10 ? r=10 ? r=50 ? r=60 ? r=60 ? r=50 ? v (tt) v (tt) c=14pf note: v (tt) = gnd t c(n) t c(n+1) t jit(cc) =t c(n) t c(n+1) figure 1. ibis model output load figure 2. output load test circuit y , fb_outc x y , fb_outt x parameter measurement information ics95v857 figure 3. cycle-to-cycle jitter
8 ics95v857-xxx preliminary product preview 0674i?03/28/03 (n is a large number of samples) t ( ) n+1 t ()n t () = 1 n=n t ()n n clk_inc clk_int fb_inc fb_int t (sk_o) y # x y , fb_outc x y , fb_outt x y , fb_outc x y , fb_outt x y , fb_outc x y , fb_outt x y x parameter measurement information figure 4. static phase offset figure 5. output skew 1 f o t = t - (jit_per) c(n) 1 f o figure 6. period jitter
9 ics95v857-xxx preliminary product preview 0674i?03/28/03 clock inputs and outputs 80% 20% 80% 20% rise t sl fall t sl v id ,v od figure 8. input and output slew rates parameter measurement information t (hper_n) t (hper_n+1) 1 f o y , fb_outc x y , fb_outt x figure 7. half-period jitter t =- (jit_hper) t (jit_hper_n) 1 2xf o
10 ics95v857-xxx preliminary product preview 0674i?03/28/03 ordering information ics95v857 y gt, ics95v857 y g-130 designation for tape and reel packaging pattern number package type g = tssop revision designator (will not correlate with datasheet revision) device type prefix ics = standard device example: ics xxxx y g - ppp - t index area index area 12 1 2 n d e1 e seating plane seating plane a1 a a2 e -c- - c - b c l aaa c 6.10 mm. body, 0.50 mm. pitch tssop (240 mil) (0.020 mil) min max min max a--1.20--.047 a1 0.05 0.15 .002 .006 a2 0.80 1.05 .032 .041 b0.170.27.007.011 c 0.09 0.20 .0035 .008 d e e1 6.00 6.20 .236 .244 e l0.450.75.018.030 n a0808 aaa -- 0.10 -- .004 variations min max min max 48 12.40 12.60 .488 .496 10-0039 n d mm. d (inch) r ef erence do c.: jedec pub li cat io n 9 5, m o- 153 0.50 basic 0.020 basic see variations see variations see variations see variations 8.10 basic 0.319 basic symbol in millimeters in inches common dimensions common dimensions
11 ics95v857-xxx preliminary product preview 0674i?03/28/03 designation for tape and reel packaging pattern number package type l = tssop (tvsop) revision designator (will not correlate with datasheet revision) device type (consists of 3 or 4 digit numbers) prefix ics = standard device example: ics xxxx y l - ppp - t index area index area 12 1 2 n d e1 e seating plane seating plane a1 a a2 e -c- - c - b c l aaa c ordering information ics95v857 yl-130 min max min max a-- 1.20 --.047 a1 0.05 0.15 .002 .006 a2 0.80 1.05 .032 .041 b 0.13 0.23 .005 .009 c 0.09 0.20 .0035 .008 d e e1 4.30 4.50 .169 .177 e l 0.45 0.75 .018 .030 n a0 8 0 8 aaa -- 0.08 -- .003 variations min max min max 48 9.60 9.80 .378 .386 10-0037 n d mm. d (inch) reference do c.: jedec p ublicatio n 95, m o-153 0.40 basic 0.016 basic see variations see variations see variations see variations 6.40 basic 0.252 basic symbol in millimeters in inches common dimensions common dimensions 4.40 mm. body, 0.40 mm. pitch tssop (173 mil) (16 mil)
12 ics95v857-xxx preliminary product preview 0674i?03/28/03 ordering information ics95v857 ykt designation for tape and reel packaging pattern number (2 or 3 digit number for parts with rom code patterns) package type k = mlf revision designator (will not correlate with datasheet revision) device type (consists of 3 or 4 digit numbers) prefix ics, av = standard device example: ics xxxx y k - ppp - t 40-pin mlf l o b m y ss n o i s n e m i d n o m m o c a- 5 8 . 00 9 . 0 1 a0 0 . 01 0 . 05 0 . 0 2 a- 5 6 . 00 8 . 0 3 af e r 0 2 . 0 dc s b 0 0 . 6 1 dc s b 5 7 . 5 ec s b 0 0 . 6 1 ec s b 5 7 . 5 q2 1 p4 2 . 02 4 . 00 6 . 0 r3 1 . 07 1 . 03 2 . 0 d n o i t a r a v h c t i p ec s b 0 5 . 0 n0 4 d n0 1 e n0 1 l0 3 . 00 4 . 00 5 . 0 b8 1 . 03 2 . 00 3 . 0 q0 0 . 00 2 . 05 4 . 0 2 d5 7 . 20 9 . 25 0 . 3 2 e5 7 . 20 9 . 25 0 . 3
13 ics95v857-xxx preliminary product preview 0674i?03/28/03 symbol min. nom. max. a 0.86 0.93 1.00 a1 0.15 0.18 0.21 a2 0.71 0.75 0.79 d 4.40 4.50 4.60 e 6.90 7.00 7.10 i j m aaa 0.10 bbb 0.10 ccc 0.10 b 0.35 0.40 0.45 e 0.625 ref. 0.575 ref. 6x10 0.65 typ. ordering information ics95v857 y ht designation for tape and reel packaging package type h = bga revision designator (will not correlate with datasheet revision) device type prefix ics = standard device example: ics xxxx y h - t 0.15 min. 0.40 dia. 0.15 typ. 1.00 max. 3 2 1 a b c d e f g h i j seating plane a1 top view e d

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